This invention relates to improvements in the quality of printed circuit board (PCB) design, application specific integrated circuit (ASIC) design and field programmable gate array (FPGA) design by using a board simulation model that is substantially identical to the board actually being fabricated to ensure that the board design will support the desired functionality, including ASIC, FPGA and other components to be mounted on the board.
In recent years, the complexity of printed circuit boards has increased rapidly. As a result, the design cycle cost tends to increase and the probability of first pass success decreases. To combat these trends, engineers are using new tools and techniques to increase the probability of first pass success. Design engineers are able to simulate entire boards or subsystems accurately, using analog or digital models of the parts. These simulations verify both the functionality of the parts and, perhaps more importantly, the interaction of the parts. Other digital design engineers may be defining the behavior of some of the board components, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). Still other engineers enter the board design in electronic design automation (EDA) tools to fabricate the board. The quality of the simulation, the ASIC and FPGA designs and the netlist that is generated by the EDA board fabrication tools can be improved by using a board simulation model that is substantially identical to the board actually being fabricated. This simulation board model can be cross checked against the fabrication board model netlist to ensure that the board design was entered correctly and to ensure that the actual board design will support the desired functionality.
In one representative embodiment, a design tool is provided that creates a hardware description language model of a printed circuit board. The design tool comprises an entry mechanism that receives part descriptions, part instances and part interconnections for the printed circuit board. A processor is connected to the entry mechanism and processes the part descriptions, part instances and part interconnections to generate an internal netlist of the printed circuit board. A compiler is connect to the processor and processes the part descriptions, the part instances and the part interconnections and the generated internal netlist to generate a hardware description language model of the printed circuit board. A netlist reader is connected to the compiler and reads a third party generated netlist of the printed circuit board. A netlist comparator is connected to the netlist reader, and the netlist comparator compares the third party generated netlist of the printed circuit board to the generated internal netlist. A report generator is connected to the netlist comparator and reports any differences between the third party generated netlist of the printed circuit board and the generated internal netlist.
In another representative embodiment, a method for creating a hardware description language model of a printed circuit board is provided. The method comprises entering part descriptions of the printed circuit board, part interconnections of the parts on the printed circuit board and part instances. An internal netlist is generated from the part descriptions, the interconnection of the parts and the part instances. An equivalence of the internal netlist to a third party generated netlist is verified. A hardware description language model of the printed circuit board is generated wherein the hardware description language model is substantially identical in connectivity to the printed circuit board.